Verification of a design is commonly used in the production of integrated circuits for bug-finding and debugging prior to manufacturing the design. Verification is typically performed by applying a test file to a device RTL model and a device reference model, where the output from each may be compared and analyzed. The test file is created by the design or verification engineer in an attempt to exercise various portions of the RTL model code during the verification process. Exercising of the code may be used to complete code coverage goals and/or functional coverage goals.
Prior to comparing the output from the RTL model and the reference model, the test file is created to accomplish code coverage goals and/or functional coverage goals. The functional coverage goals must be specified by the design or verification engineer. Conventional methods of creating test files involve the design or verification engineer writing an initial test file and simulating processing of the test file by the RTL model. Based upon the results of the simulation, the design or verification engineer then writes another test file to increase the code and/or functional coverage of the test file. This process is typically repeated many times until the set of test files is acceptable, or resources allocated to the test file generation effort are expended.
As such, conventional methods for creating test files are very time consuming and costly. Additionally, test files created by conventional methods often provide inadequate code coverage given the extensive skill and experience required to create an acceptable test file using conventional methods of generating test files. Further, inadequate functional coverage is common with conventional methods of generating test files since the design or verification engineer must not only specify functional coverage goals which requires skill and experience, but also write a test file which covers the specified goals.